kpit.h

00001 /***************************************************************************
00002                           kpit.h  -  description
00003                              -------------------
00004     begin                : Sat Jan 2 2004
00005     copyright            : (C) 2003 by Dynacube Team
00006     email                : mdshah82@yahoo.com
00007  ***************************************************************************/
00008 
00009 /***************************************************************************
00010  *                                                                         *
00011  *   This program is free software; you can redistribute it and/or modify  *
00012  *   it under the terms of the GNU General Public License as published by  *
00013  *   the Free Software Foundation; either version 2 of the License, or     *
00014  *   (at your option) any later version.                                   *
00015  *                                                                         *
00016  ***************************************************************************/
00017 
00018 #ifndef __KPIT_H
00019 #define __KPIT_H
00020 
00021         #include "common/ktypes.h"
00022         
00023 /*
00024 8253/8254 PIT - Programmable Interval Timer 
00025         Port 40h, 8253 Counter 0 Time of Day Clock (normally mode 3)
00026         Port 41h, 8253 Counter 1 RAM Refresh Counter (normally mode 2)
00027         Port 42h, 8253 Counter 2 Cassette and Speaker Functions
00028         Port 43h, 8253 Mode Control Register, data format:
00029 
00030         |7|6|5|4|3|2|1|0|  Mode Control Register
00031          | | | | | | | +---- 0=16 binary counter, 1=4 decade BCD counter
00032          | | | | +--------- counter mode bits
00033          | | +------------ read/write/latch format bits
00034          +--------------- counter select bits (also 8254 read back command)
00035 Bits 
00036          76 Counter Select Bits
00037          00  select counter 0
00038          01  select counter 1
00039          10  select counter 2
00040          11  read back command (8254 only, illegal on 8253, see below)
00041 Bits 
00042          54  Read/Write/Latch Format Bits
00043          00  latch present counter value
00044          01  read/write of MSB only
00045          10  read/write of LSB only
00046          11  read/write LSB, followed by write of MSB
00047 Bits 
00048         321  Counter Mode Bits
00049         000  mode 0, interrupt on terminal count;  countdown, interrupt,
00050              then wait for a new mode or count; loading a new count in the
00051              middle of a count stops the countdown
00052         001  mode 1, programmable one-shot; countdown with optional
00053              restart; reloading the counter will not affect the countdown
00054              until after the following trigger
00055         010  mode 2, rate generator; generate one pulse after 'count' CLK
00056              cycles; output remains high until after the new countdown has
00057              begun; reloading the count mid-period does not take affect
00058              until after the period
00059         011  mode 3, square wave rate generator; generate one pulse after
00060              'count' CLK cycles; output remains high until 1/2 of the next
00061              countdown; it does this by decrementing by 2 until zero, at
00062              which time it lowers the output signal, reloads the counter
00063              and counts down again until interrupting at 0; reloading the
00064              count mid-period does not take affect until after the period
00065         100  mode 4, software triggered strobe; countdown with output high
00066              until counter zero;  at zero output goes low for one CLK
00067              period;  countdown is triggered by loading counter;  reloading
00068              counter takes effect on next CLK pulse
00069         101  mode 5, hardware triggered strobe; countdown after triggering
00070              with output high until counter zero; at zero output goes low
00071              for one CLK period
00072 */      
00073 
00074         #define PIT_FREQ            0x12378E  //In Hertz (equal 1.19318 MHz)
00075 
00076         #define PIT_PORT_0    0x40
00077         #define PIT_PORT_1    0x41
00078         #define PIT_PORT_2    0x42
00079         #define PIT_MCR_PORT  0x43
00080 
00081         //Counter Selection Bits
00082         #define PIT_COUNTER_0 0x00
00083         #define PIT_COUNTER_1 0x40
00084         #define PIT_COUNTER_2 0x80
00085 
00086         //Read/Write/Latch Format Bits 
00087         #define LATCH           0x00
00088         #define RW_MSB_ONLY     0x10
00089         #define RW_LSB_ONLY     0x20
00090         #define RW_LSB_MSB      0x30    
00091 
00092         //Counter Mode Bits
00093         #define MODE_0          0x0
00094         #define MODE_1          0x2
00095         #define MODE_2          0x4
00096         #define MODE_3          0x6
00097         #define MODE_4          0x8
00098         #define MODE_5          0x10
00099         
00100         //Counter Base Type
00101         #define BINARY  0x0
00102         #define BCD             0x1
00103 
00104         void pit0_init(DD num_of_times);
00105         void pit1_init();
00106         void pit2_init();
00107 
00108 #endif

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